Day 1 - Introduction to Verilog RTL design and Synthesis

SKY130RTL D1SK1 L1 Introduction to iverilog design test bench

In the first lecture of the course, we learnt about the definitions of the RTL Design, Simulator and Test Bench. The simulator we are going to use in this workshop is iverilog. After the definitions of the terms mentioned above, we learnt the workings of Simulator and Test Bench.

Simulator Working:

Simulator looks for the changes in the input and for every change in the input, we observe changes in the output.

Test Bench:

Test Bench generates the stimulus for the design and observes the output.

iverilog based simulator flow:

iverilog simulator takes the design and corresponding test bench of the design and generates the vcd( Value Change Dump format) file. The vcd file can be viewed using gtkwave waveform viewer.

SKY130RTL D1SK2 - Labs using iverilog and gtkwave SKY130RTL D1SK2 L1 Lab1 introduction to lab:

In this session we git cloned the required modules from GitHub to VLSI foldr

Inside the sky130 folder we have my lib which contains the standard cell library sky130_fd_sc_hd tt_025C_1v80.lib

All the required Verilog files and Test benches are present in Verilog files folder.

SKY130RTL D1SK2 L2 Lab2 Introduction iverilog gtkwave part1:

In this lab, we learnt how to simulate Verilog files using iverilog. After executing the a.out file we get the dumpfile, which can be used using GTKWAVE waveform user.

SKY130RTL D1SK2 L3 Lab2 Introduction iverilog gtkwave part2:

In this module, we have seen how to open verilog file using gvim command.

SKY130RTL D1SK3 - Introduction to Yosys and Logic synthesis

SKY130RTL D1SK3 L1 Introduction to yosys:

Synthesizer:

It is a tool used for converting the RTL into netlist. In this workshop we are going to use yosys synthesizer.

Yosys setup:

Verification of the synthesis:

To verify the generated netlist, we are going to use the same test bench and iverilog simulator.

SKY130RTL D1SK3 L2 introduction to logic synthesis part1

RTL Design:

SYNTHESIS:

.lib:

.lib is a collection of logic modules, which include basic logic gates and different flavours of same gates.

Why do we have different flavours of gates?

In order to have time for the logic to be executed properly and for setting up and holding of the current and previous inputs and outputs, we need different flavours of gates.

For example, consider this situation:

In this situation the clock should accommodate the propagation delay, combinational logic delay and setup time of the B D flipflop. As the time is inversely proportional to frequency the smaller the time the faster the frequency. If we have faster cells, the time taken for the operation will be less. Less time implies maximum frequency.

SKY130RTL D1SK3 L3 introduction to logic synthesis part2:

Why do we need slower cells?

In order to have proper hold time for the newly generated values in the design. If we go too fast, the logic may miss few values and we won’t get the intended results.

FASTER CELLS VS SLOWER CELLS:

SYNTHESIS:

After syntactical check, the synthesizer will map different types of statements in the code to standard cells as shown below.

SKY130RTL D1SK4 L1 Lab3 Yosys 1 good mux Part1:

yosys:

yosys can be invoked by using the command yosys in the Verilog files module.

Reading the liberty:

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

Command: read_verilog good_mux.v

Reads the good_mux verilog file.

Command: synth –top good_mux

Specifies the modules to be synthesized and synthesizes the module.

Commnad: abc -liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib

This command generates netlist based on the standard cells available in the library.

Command: show

Displays the graphical version of the netlist in dot viewer.

SKY130RTL D1SK4 L2 Lab3 Yosys 1 good mux Part2:

In older version of yosys the above synthesis will generate two inverse gates and Nand for the function of and. But in the latest version directly a mux is used as standard cell.

SKY130RTL D1SK4 L3 Lab3 Yosys 1 good mux Part3:

Command: write_verilog good_mux_netlist.v

Command: !gvim good_mux_netlsit.v Reads the netlist.

Command: write_verilog –noattr good_mux_netlist.v

!gvim goof_mux_netlsit.v To make the netlsit readable.

DAY 2:

SKY130RTL D2SK1 L1 Lab4 Introduction to dot :

Command: gvim ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

The various terms of the opened library’s name are tt-> typical process ,025C-> Temperature, 1v80-

>voltage.

SKY130RTL D2SK2 L1 Lab05 Hier synthesis flat synthesis part1: HEIRARCHIAL SYNTHESIS OF MULTIPLE_MODULES

Command: gvim multiple_modules.v

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog multiple_modules.v

Command: synth –top multiple_modules

Commnad: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib

Command: show multiple_modules HEIRARICHAL SYNTHESIS

Command: write_verilog –noattr multiple_modules_netlsit.v Command: !gvim multiple_modules_netlist.v

FLAT SYNTHESIS OF MULTIPLE_MOUDLES:

Command: flatten

Command: write_verilog –noattr multiple_modules_flat.v Command: !gvim multiple modules_flat.v

Command: show multiple_modules

SYNTHESIS OF INDIVIDUAL MODULES:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog multiple_modules.v

Command: synth –top sub_module1

Command: abc –liberty ../my-lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show sub_module1

Command: write –noattr sub_moudle_netlist.v Command: !gvim sub_module_netlist.v

SKY130RTL D2SK3 L3 Lab flop synthesis simulations part1: DFF_ASYNCRES IVERILOG SIMULATION

Command: iverilog dff_asyncres.v tb_dff_asyncres.v Command: ./a.out

Command: gtkwave tb_dff_asyncres.vcd

OBSERVATIONS: If there is no reset, the state changes only with posedge of clock.

Else, the output changes with reset.

DFF_ASYNC_SET IVERILOG SIMULATION:

Command: iverilog dff_async_set.v tb_dff_async_set.v Command: ./a.out

Command: gtkwave tb_dff_async_set.vcd

OBSERVATIONS: The q will be set without waiting for the clock. The q value will wait till the posedge of clock.

DFF_SYNCRES IVERILOG SIMULATION:

Command: iverilog dff_syncres.v tb_dff_syncres.v Command: ./a.out

Command: gtkwave tb_dff_syncres.vcd

OBSERVATIONS: The q will change only with the posedge of the clock even when the sync_reset is on.

SKY130RTL D2SK3 L4 Lab flop synthesis simulations part2: DFF_ASYNCRES SYNTHESIS:

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_ayncres.v

Command: synth –top dff_asyncres

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib This command helps if the flop library and standard cell library are different.

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib

Command: show

OBSERVATIONS: The use of inverse gate in the synthesis indicates that the flop, in the library, has active low reset as input.

DFF_ASYNC_SET SYNTHESIS:

Command: read_verilog dff_async_set.v Command: synth –top dff_async_set

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

DFF_SYNCRES SYNTHESIS:

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_syncres.v

Command: synth –top dff_syncres

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

SKY130RTL D2SK3 L5 Interesting optimisations part1:

Command: gvim mult_*.v -o

This command helps in opening multiple files, with mult as starting four letters.

OBSERVATIONS:

The first file mult_2.v gives 4-bit output after multiplication of 2 and 3-bit input.
The output is nothing but appending a ‘0’ at the right side of the input.
The second file mult_8.v gives 6-bit output after multiplication of 9 and 3-bit input. The output can be generated by appending the input with itself.

MULT_2 SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog mult_2.v

Command: synth –top mul2

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS:

The print statistics indicates that no cells are required.
The netlist generation command shows “there is nothing to map”.

Command: show

OBSERVATION: As discussed before, the result is generated by appending the zero at right side. Command: write_verilog –noattr mult_2_netlist.v

Command: !gvim mult_2_netlist.v

MULT_8 SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog mult_8.v

Command: synth –top mult8

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: There are no standard cells used in this synthesis.

OBSERVATIONS: The abc command doesn’t want to be called without standard cells.

OBSERVATIONS: The show command indicates that the input is appended to itself and given as output.

Command : write_verilog mult_8_netlsit.v Command: !gvim mult_8_netlsit.v

DAY 3:

SKY130RTL D3SK2 L1 Lab06 Combinational Logic Optimisations part1: OPT_CHECK OPTIMISZATION AND SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog opt_check.v

Command: synth –top opt_check

Command: opt_clean –purge

This command helps in identifying and removing the unused cells in the design.

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS:

1) When one of the inputs of a multiplexer is zero, the design can be optimised as an AND gate.

OPT_CHECK2 OPTIMISZATION AND SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog opt_check2.v

Command: synth –top opt_check2

Command: opt_clean –purge

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS:

When one of the inputs of multiplexer is one, the design can be optimised as a OR gate.
Instead of generating OR gate from Nand gates, the updated standard cell library had an OR gate.

SKY130RTL D3SK2 L2 Lab06 Combinational Logic Optimisations part2:

OPT_CHECK3 OPTIMIZATION AND SYNTHESIS :

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog opt_check3.v

Command: synth –top opt_check3

Command: opt_clean –purge

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: The two multiplexers in the opt_check3.v are optimised as single 3 input AND gate. Because, one the inputs of the two multiplexers are zero they are optimised to AND gates as in opt_check.v.

OPT_CHECK4.V OPTIMISATION AND SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog opt_check4.v

Command: synth –top opt_check4 Command: opt_clean –purge

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: The opt_check4.v design is simplified as an XNOR gate.

MULTIPLE_MODULE_OPT.V OPTIMIZATION AND SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog multiple_module_opt.v

Command: synth –top multiple_module_opt Command: flatten

Command: opt_clean –purge

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

Command: write_verilog –noattr multiple_module_opt_netlist.v Command: !gvim multiple_module_opt_netlist.v

OBSERVATIONS:

The multiple_module_opt.v is optimised to a two input AND gate and two input OR gate using boolean logic optimization.
The U1 module is simplified to a.

MULTIPLE_MODULE_OPT2.V OPTIMIZATION AND SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog multiple_module_opt.v

Command: synth –top multiple_module_opt2 Command: flatten

Command: opt_clean –purge

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

Command: write_verilog –noattr multiple_module_opt2_netlist.v Command: !gvim multiple_module_module_opt2_netlist.v

OBSERVATIONS:

The synthesizer optimised the multiple_module_opt2.v using constant propagation optimization.
The synthesizer optimized the output to zero.

SKY130RTL D3SK3 L1 Lab07 Sequential Logic Optimisations part1: DFF_CONST1 SIMULATION:

Command: iverilog dff_const1.v tb_dff_const1.v Command: ./a.out

Command: gtkwave tb_dff_const1.vcd

OBSERVATIONS: The q doesn’t change value when reset is low. Q will change value only with the

posedge of the clock.

DFF_CONST2 SIMULATION:

Command: iverilog dff_const1.v tb_dff_const2.v Command: ./a.out

Command: gtkwave tb_dff_const2.vcd

OBSERVATIONS: The q value is always one.

DFF_CONST1.V SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const1.v

Command: synth –top dff_const1

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: As stated before, the D_flip_flop in the netlist is active_low. So, the synthesizer used an inverter to change rest from active_high to active_low.

SKY130RTL D3SK3 L2 Lab07 Sequential Logic Optimisations part2: DFF_CONST2.V SYNTHESIS

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const2.v

Command: synth –top dff_const2

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATION: ABC command ‘s result is indicating that there is no standard cell.

SKY130RTL D3SK3 L2 Lab07 Sequential Logic Optimisations part3:

DFF_CONST3.V SIMULATION, OPTIMIZATION AND SYNTHESIS:

Command: iverilog dff_const3.v tb_dff_const3.v Command: ./.aout

Command: gtkwave tb_dff_const3.vcd

OBSERVATIONS: q=1 at every instant except at the moment in the above figure. So, the flipflop can’t

be optimised.

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const3.v

Command: synth –top dff_const3

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: Because q cannot be optimised, the circuit remains unoptimized.

DFF_CONST4.V SIMULATION, OPTIMIZATION AND SYNTHESIS:

Command: iverilog dff_const4.v tb_dff_const4.v Command: ./.aout

Command: gtkwave tb_dff_const4.vcd

OBSERVATIONS: The q is always one. Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const4.v

Command: synth –top dff_const4

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: As the q is always one in this synthesis, there is no standard cell in the netlist.

DFF_CONST5.V SIMULATION, OPTIMIZATION AND SYNTHESIS:

Command: iverilog dff_const5.v tb_dff_const5.v Command: ./.aout

Command: gtkwave tb_dff_const5.vcd

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const4.v

Command: synth –top dff_const4

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: There is no optimization in this file synthesis.

SKY130RTL D3SK4 L1 Seq optimisation unused outputs part1: COUNTER_OPT.V SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog counter_opt.v

Command: synth –top counter_opt

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: The synthesis shows that q is connected to D through an inverter. So, for every posedge, they q will change. The synthesizer will ignore the counting of the remaining two bits.

SKY130RTL D3SK4 L2 Seq optimisation unused outputs part2: COUNTER_OPT2.V SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog counter_opt2.v

Command: synth –top counter_opt

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: There is no optimization in this synthesis.

COUNTER_OPT3.V SYNTHESIS FOR ASSESMENT:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog counter_opt3.v

Command: synth –top counter_opt

Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

DAY 4:

SKY130RTL D4SK2 L1 Lab GLS Synth Sim Mismatch part1: TERENARY_OPERATOR GLS :

Command: iverilog ternary_operator_mux.v tb_ternary_operator_mux.v Command: ./a.out

Command: gtkwave tb_ternary_operator_mux.vcd

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib

Command: read_verilog ternary_operator_mux.v Command: synth –top ternary_operator_mux

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

Command: write_verilog –noattr ternary_operator_mux_net.v

Command: iverilog ../my_lib/verilog_model/primitives.v ../my_lib/verilog_model/sky130_fd_sc_hd.v ternary_operator_mux_net.v tb_ternary_operator_mux.v

Command: ./a.out

Command: gtkwave tb_ternary_operator_mux.v

SKY130RTL D4SK2 L2 Lab GLS Synth Sim Mismatch part2: BAD_MUX.V SIMULATION:

Command: iverilog bad_mux.v tb_bad_mux.v Command: ./a.out

Command: gtkwave tb_bad_mux.vcd

OBSERVTIONS: Clearly, the waveform shows that the verilog file is not working as a multiplexer.

BAD_MUX.V Synthesis:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog bad_mux.v

Command: synth –top bad_mux

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: write_verilog –noattr bad_mux_net.v

Command: iverilog ../my_lib/verilog_module/primitives.v

../my_lib/verilog_model/sky130_fd_sc_hd.v bad_mux.net.v tb_bad_mux.v Command: ./a.out

Command: gtkwave tb_bad_mux.vcd

OBSERVATION: THE ABOVE WAVEFORM CLEARLY INDICATES SIMULATION – SYNTHESIS MISMATCH CAUSED BY MISSING SENSITIVITY LIST.

SKY130RTL D4SK3 L1 Lab Synth sim mismatch blocking statement part1: BLOCKING CAVEAT.V SIMULATION

Command: iverilog blocking_caveat.v tb_blocking_caveat.v Command: ./a.out

Command: gtkwave tb_blocking_caveat.vcd

OBSERVATIONS: Clearly, the output of the aORb is taking previous values to generate d.

SKY130RTL D4SK3 L1 Lab Synth sim mismatch blocking statement part2: BLOCKING CAVEAT.V SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog blocking_caveat.v

Command: synth –top blocking_caveat

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: write_verilog –noattr bad_mux_net.v

Command: iverilog ../my_lib/verilog_module/primitives.v

../my_lib/verilog_model/sky130_fd_sc_hd.v blocking_caveat_net.v tb_blocking_caveat.v Command: ./a.out

Command: gtkwave tb_blocking_caveat.vcd

OBSERVATION: Clearly, the waveform after synthesis indicates the simulation-synthesis mismatch caused by blocking-caveat.

DAY 5:

SKY130RTL D5SK2 L1 Lab Incomplete IF part1: INCOMPLETE_IF SIMULATION:

Command: iverilog incomp_if.v tb_incomp_if.v Command: ./a.out

Command: gtkwave tb_incomp_if.vcd

OBSERVATIONS:

Whenever i0 is high, the y is following i1.
Whenever i0 is low, the output y is latching to its previous value as shown in above two images. 3)This behaviour is due to inferred latch.

INCOMP_IF SYNTHESIS:
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog incomp_if.v
Command: synth –top incomp_if
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib
Command: show

OBSERVATIONS: Both the simulation and synthesis are inferring a latch, when we designed a multiplexer.

SKY130RTL D5SK2 L2 Lab Incomplete IF part2: INCOMPLETE_IF SIMULATION2:
Command: iverilog incomp_if2.v tb_incomp_if2.v Command: ./a.out
Command: gtkwave tb_incomp_if2.vcd

OBSERVATIONS:
1. When i0 is high, the output y is following i1.
2. When i2 is high and i1 is low, the output is following i2.
3. When both i2 and i0 are low, the output is latching to y.

INCOMP_IF2 SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog incomp_if2.v

Command: synth –top incomp_if2

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS:

Clearly, we can see the inferred latch on dot viewer.
The D_latch has active high enable. So, when i0 and i1 are low, the output of the nor gate becomes high. Then the latch becomes active.
SKY130RTL D5SK3 L1 Lab incomplete overlapping Case part1: INCOMP_CASE SIMUALTION:
Command: iverilog incomp_case.v tb_incomp_case.v Command: ./a.out
Command: gtkwave tb_incomp_case.vcd

OBSERVATIONS:
1. The output y is i0 when select is 00. When the select is 01, the output y is i1.
2. When the select bit [1] is high, the circuit latches to y value. In this y is zero.

INCOMP_CASE SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog incomp_case.v

Command: synth –top incomp_case

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS:

1)The dot viewer is showing the latch with enable tied to select [1]. 2)The remaining part is the mux logic.

SKY130RTL D5SK3 L2 Lab incomplete overlapping Case part2: COMP_CASE SIMUALTION:

Command: iverilog comp_case.v tb_comp_case.v Command: ./a.out

Command: gtkwave tb_comp_case.vcd

OBSERVATIONS: The output y is following y when select is 10 or 11.

COMP_CASE SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog comp_case.v

Command: synth –top comp_case

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS: Clearly, there is no latch and circuit is working fine in both simulation and synthesis.

SKY130RTL D5SK3 L3 Lab incomplete overlapping Case part3: PARTIAL_CASE_ASSIGN SIMULATION:

Command: iverilog partial_case_assign.v tb_partial_case_assign.v Command: ./a.out

Command: gtkwave tb_partial_case_assign.vcd

OBSERVATION: Clearly, when select is 01, the x is latching to its value.

PARTIAL_CASE_ASSIGN SYNHTESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog partial_case_assign.v

Command: synth –top partial_case_assign

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATIONS:

1) The dot viewer clearly shows the latch for x and there is no latch for y.

BAD_CASE SIMULATION:

Command: iverilog bad_case.v tb_bad_case.v Command: ./a.out

Command: gtkwave tb_bad_case.vcd

OBSERVATION: Clearly, when the select is 11, the output y is becoming 1.

SKY130RTL D5SK3 L4 Lab incomplete overlapping Case part4: BAD_CASE SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog bad_case.v

Command: synth –top bad_case

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

Observation: There are no latches in bad_case.

BAD_MUX NETLSIT SIMULATION:

Command: write_verilog –noattr tb_bad_case_net.v

Command: iverilog ../my_lib/verilog_model/primitives.v ../my_lib/verilog_model/sky130_fd_sc_hd.v bad_case_net.v tb_bad_case.v

Command: ./a.out

Command: gtkwave tb_bad_case.vcd

OBSERVATION:

The netlist simulations shows that the output y is taking i3, when the select is 11.
This is a simulation-synthesis mismatch. So, we need to avoid overlapping case while VERILOG coding.

SKY130RTL D5SK5 L1 Lab For and For Generate part1: MUX_GENERATE.V SIMULATION:

Command: iverilog mux_generate.v tb_mux_generate.v Command: ./a.out

Command: gtkwave tb_mux_generate.vcd

OBSERVATION: We can see the waveforms of a 4:1 mulitplexer designed using for loop.

MUX_GENERATE.V SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog mux_generate.v

Command: synth –top mux_generate

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATION: We can see that the synthesis has a latch. The latch just acts as a buffer.

SKY130RTL D5SK5 L2 Lab For and For Generate part2: DEMUX_CASE SIMULATION:

Command: iverilog demux_case.v tb_demux_case.v Command: ./a.out

Command: gtkwave tb_demux_case.vcd

OBSERVATION: We can see that output is being selected based on the select line.

DEMUX_CASE SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog demux_case.v

Command: synth –top demux_case

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

DEMUX_GENERATE.V SIMULATION:

Command: iverilog demux_generate.v tb_demux_generate.v Command: ./a.out

Command: gtkwave tb_demux_generate.vcd

DEMUX_GENERATE SYNTHESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog demux_generate.v

Command: synth –top demux_generate

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show

OBSERVATION: In this lab, both demux_case.v and demux_generate.v has similar synthesis. However, the demux_generate.v can be scalable.

SKY130RTL D5SK5 L3 Lab For and For Generate part3:

Command: gvim rca.v -o fa.v

SKY130RTL D5SK5 L4 Lab For and For Generate part4:

RCA SIMULATION:

Command: iverilog fa.v rca.v tb_rca.v

This command tells the simulator that fa.v is separate module but is called in rca.v. Command: ./a.out

Command: gtkwave tb_rca.vcd

RCS SYNHTESIS:

Command: yosys

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog fa.v

Command: read_verilog rca.v Command: synth –top rca

Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show rca

OBSERVATION: 8 FA MODULES ARE INSTANTIATED.

RCA GLS SYNHTESIS:

Command: write_verilog –noattr tb_rca_net.v

Command: iverilog ../my_lib/verilog_module/primitives.v

../my_lib/verilog_model/sky130_fd_sc_hd.v tb_rca_net.v tb_rca.v Command: ./a.out

Command: gtkwave tb_rca.vcd

OBSERVATIONS: There is no mismatch between simulation and synthesis.

Simulator Working:

Test Bench:

iverilog based simulator flow:

SKY130RTL D1SK2 L2 Lab2 Introduction iverilog gtkwave part1:

SKY130RTL D1SK2 L3 Lab2 Introduction iverilog gtkwave part2:

SKY130RTL D1SK3 L1 Introduction to yosys:

Synthesizer:

Yosys setup:

Verification of the synthesis:

SKY130RTL D1SK3 L2 introduction to logic synthesis part1

RTL Design:

SYNTHESIS:

.lib:

Why do we have different flavours of gates?

SKY130RTL D1SK3 L3 introduction to logic synthesis part2:

Why do we need slower cells?

FASTER CELLS VS SLOWER CELLS:

SYNTHESIS:

SKY130RTL D1SK4 L1 Lab3 Yosys 1 good mux Part1:

yosys:

Reading the liberty:

Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

Command: read_verilog good_mux.v

SKY130RTL D1SK4 L2 Lab3 Yosys 1 good mux Part2:

SKY130RTL D1SK4 L3 Lab3 Yosys 1 good mux Part3:

Command: write_verilog –noattr good_mux_netlist.v

SKY130RTL D2SK1 L1 Lab4 Introduction to dot :

SKY130RTL D2SK2 L1 Lab05 Hier synthesis flat synthesis part1: HEIRARCHIAL SYNTHESIS OF MULTIPLE_MODULES

Command: gvim multiple_modules.v

FLAT SYNTHESIS OF MULTIPLE_MOUDLES:

SYNTHESIS OF INDIVIDUAL MODULES:

SKY130RTL D2SK3 L3 Lab flop synthesis simulations part1: DFF_ASYNCRES IVERILOG SIMULATION

DFF_ASYNC_SET IVERILOG SIMULATION:

DFF_SYNCRES IVERILOG SIMULATION:

SKY130RTL D2SK3 L4 Lab flop synthesis simulations part2: DFF_ASYNCRES SYNTHESIS:

DFF_ASYNC_SET SYNTHESIS:

DFF_SYNCRES SYNTHESIS:

SKY130RTL D2SK3 L5 Interesting optimisations part1:

MULT_2 SYNTHESIS:

MULT_8 SYNTHESIS:

SKY130RTL D3SK2 L1 Lab06 Combinational Logic Optimisations part1: OPT_CHECK OPTIMISZATION AND SYNTHESIS:

OPT_CHECK2 OPTIMISZATION AND SYNTHESIS:

Command: opt_clean –purge

SKY130RTL D3SK2 L2 Lab06 Combinational Logic Optimisations part2:

OPT_CHECK3 OPTIMIZATION AND SYNTHESIS :

OPT_CHECK4.V OPTIMISATION AND SYNTHESIS:

MULTIPLE_MODULE_OPT.V OPTIMIZATION AND SYNTHESIS:

MULTIPLE_MODULE_OPT2.V OPTIMIZATION AND SYNTHESIS:

SKY130RTL D3SK3 L1 Lab07 Sequential Logic Optimisations part1: DFF_CONST1 SIMULATION:

DFF_CONST2 SIMULATION:

DFF_CONST1.V SYNTHESIS:

SKY130RTL D3SK3 L2 Lab07 Sequential Logic Optimisations part2: DFF_CONST2.V SYNTHESIS

SKY130RTL D3SK3 L2 Lab07 Sequential Logic Optimisations part3:

DFF_CONST3.V SIMULATION, OPTIMIZATION AND SYNTHESIS:

DFF_CONST4.V SIMULATION, OPTIMIZATION AND SYNTHESIS:

DFF_CONST5.V SIMULATION, OPTIMIZATION AND SYNTHESIS:

SKY130RTL D3SK4 L1 Seq optimisation unused outputs part1: COUNTER_OPT.V SYNTHESIS:

SKY130RTL D3SK4 L2 Seq optimisation unused outputs part2: COUNTER_OPT2.V SYNTHESIS:

COUNTER_OPT3.V SYNTHESIS FOR ASSESMENT:

SKY130RTL D4SK2 L1 Lab GLS Synth Sim Mismatch part1: TERENARY_OPERATOR GLS :

SKY130RTL D4SK2 L2 Lab GLS Synth Sim Mismatch part2: BAD_MUX.V SIMULATION:

BAD_MUX.V Synthesis:

SKY130RTL D4SK3 L1 Lab Synth sim mismatch blocking statement part1: BLOCKING CAVEAT.V SIMULATION

SKY130RTL D4SK3 L1 Lab Synth sim mismatch blocking statement part2: BLOCKING CAVEAT.V SYNTHESIS:

SKY130RTL D5SK2 L1 Lab Incomplete IF part1: INCOMPLETE_IF SIMULATION:

INCOMP_IF SYNTHESIS:

SKY130RTL D5SK2 L2 Lab Incomplete IF part2: INCOMPLETE_IF SIMULATION2:

INCOMP_IF2 SYNTHESIS:

SKY130RTL D5SK3 L1 Lab incomplete overlapping Case part1: INCOMP_CASE SIMUALTION:

INCOMP_CASE SYNTHESIS:

SKY130RTL D5SK3 L2 Lab incomplete overlapping Case part2: COMP_CASE SIMUALTION:

COMP_CASE SYNTHESIS:

SKY130RTL D5SK3 L3 Lab incomplete overlapping Case part3: PARTIAL_CASE_ASSIGN SIMULATION:

PARTIAL_CASE_ASSIGN SYNHTESIS:

BAD_CASE SIMULATION:

SKY130RTL D5SK3 L4 Lab incomplete overlapping Case part4: BAD_CASE SYNTHESIS:

BAD_MUX NETLSIT SIMULATION:

SKY130RTL D5SK5 L1 Lab For and For Generate part1: MUX_GENERATE.V SIMULATION:

MUX_GENERATE.V SYNTHESIS:

SKY130RTL D5SK5 L2 Lab For and For Generate part2: DEMUX_CASE SIMULATION: