Day 1 - Introduction to Verilog RTL design and Synthesis
SKY130RTL D1SK1 L1 Introduction to iverilog design test bench
In the first lecture of the course, we learnt about the definitions of the RTL Design, Simulator and Test Bench. The simulator we are going to use in this workshop is iverilog. After the definitions of the terms mentioned above, we learnt the workings of Simulator and Test Bench.
Simulator looks for the changes in the input and for every change in the input, we observe changes in the output.
Test Bench generates the stimulus for the design and observes the output.
iverilog simulator takes the design and corresponding test bench of the design and generates the vcd( Value Change Dump format) file. The vcd file can be viewed using gtkwave waveform viewer.
SKY130RTL D1SK2 - Labs using iverilog and gtkwave SKY130RTL D1SK2 L1 Lab1 introduction to lab:
In this session we git cloned the required modules from GitHub to VLSI foldr
Inside the sky130 folder we have my lib which contains the standard cell library sky130_fd_sc_hd tt_025C_1v80.lib
All the required Verilog files and Test benches are present in Verilog files folder.
In this lab, we learnt how to simulate Verilog files using iverilog. After executing the a.out file we get the dumpfile, which can be used using GTKWAVE waveform user.
In this module, we have seen how to open verilog file using gvim command.
SKY130RTL D1SK3 - Introduction to Yosys and Logic synthesis
It is a tool used for converting the RTL into netlist. In this workshop we are going to use yosys synthesizer.
To verify the generated netlist, we are going to use the same test bench and iverilog simulator.
.lib is a collection of logic modules, which include basic logic gates and different flavours of same gates.
In order to have time for the logic to be executed properly and for setting up and holding of the current and previous inputs and outputs, we need different flavours of gates.
For example, consider this situation:
In this situation the clock should accommodate the propagation delay, combinational logic delay and setup time of the B D flipflop. As the time is inversely proportional to frequency the smaller the time the faster the frequency. If we have faster cells, the time taken for the operation will be less. Less time implies maximum frequency.
In order to have proper hold time for the newly generated values in the design. If we go too fast, the logic may miss few values and we won’t get the intended results.
After syntactical check, the synthesizer will map different types of statements in the code to standard cells as shown below.
yosys can be invoked by using the command yosys in the Verilog files module.
Reads the good_mux verilog file.
Command: synth –top good_mux
Specifies the modules to be synthesized and synthesizes the module.
Commnad: abc -liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib
This command generates netlist based on the standard cells available in the library.
Command: show
Displays the graphical version of the netlist in dot viewer.
In older version of yosys the above synthesis will generate two inverse gates and Nand for the function of and. But in the latest version directly a mux is used as standard cell.
Command: write_verilog good_mux_netlist.v
Command: !gvim good_mux_netlsit.v Reads the netlist.
!gvim goof_mux_netlsit.v To make the netlsit readable.
DAY 2:
Command: gvim ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
The various terms of the opened library’s name are tt-> typical process ,025C-> Temperature, 1v80-
>voltage.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog multiple_modules.v
Command: synth –top multiple_modules
Commnad: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib
Command: show multiple_modules HEIRARICHAL SYNTHESIS
Command: write_verilog –noattr multiple_modules_netlsit.v Command: !gvim multiple_modules_netlist.v
Command: flatten
Command: write_verilog –noattr multiple_modules_flat.v Command: !gvim multiple modules_flat.v
Command: show multiple_modules
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog multiple_modules.v
Command: synth –top sub_module1
Command: abc –liberty ../my-lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show sub_module1
Command: write –noattr sub_moudle_netlist.v Command: !gvim sub_module_netlist.v
Command: iverilog dff_asyncres.v tb_dff_asyncres.v Command: ./a.out
Command: gtkwave tb_dff_asyncres.vcd
OBSERVATIONS: If there is no reset, the state changes only with posedge of clock.
Else, the output changes with reset.
Command: iverilog dff_async_set.v tb_dff_async_set.v Command: ./a.out
Command: gtkwave tb_dff_async_set.vcd
OBSERVATIONS: The q will be set without waiting for the clock. The q value will wait till the posedge of clock.
Command: iverilog dff_syncres.v tb_dff_syncres.v Command: ./a.out
Command: gtkwave tb_dff_syncres.vcd
OBSERVATIONS: The q will change only with the posedge of the clock even when the sync_reset is on.
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_ayncres.v
Command: synth –top dff_asyncres
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib This command helps if the flop library and standard cell library are different.
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib
Command: show
OBSERVATIONS: The use of inverse gate in the synthesis indicates that the flop, in the library, has active low reset as input.
Command: read_verilog dff_async_set.v Command: synth –top dff_async_set
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_syncres.v
Command: synth –top dff_syncres
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
Command: gvim mult_*.v -o
This command helps in opening multiple files, with mult as starting four letters.
OBSERVATIONS:
The first file mult_2.v gives 4-bit output after multiplication of 2 and 3-bit input.
The output is nothing but appending a ‘0’ at the right side of the input.
The second file mult_8.v gives 6-bit output after multiplication of 9 and 3-bit input. The output can be generated by appending the input with itself.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog mult_2.v
Command: synth –top mul2
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS:
The print statistics indicates that no cells are required.
The netlist generation command shows “there is nothing to map”.
Command: show
OBSERVATION: As discussed before, the result is generated by appending the zero at right side. Command: write_verilog –noattr mult_2_netlist.v
Command: !gvim mult_2_netlist.v
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog mult_8.v
Command: synth –top mult8
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: There are no standard cells used in this synthesis.
OBSERVATIONS: The abc command doesn’t want to be called without standard cells.
OBSERVATIONS: The show command indicates that the input is appended to itself and given as output.
Command : write_verilog mult_8_netlsit.v Command: !gvim mult_8_netlsit.v
DAY 3:
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog opt_check.v
Command: synth –top opt_check
Command: opt_clean –purge
This command helps in identifying and removing the unused cells in the design.
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS:
1) When one of the inputs of a multiplexer is zero, the design can be optimised as an AND gate.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog opt_check2.v
Command: synth –top opt_check2
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS:
When one of the inputs of multiplexer is one, the design can be optimised as a OR gate.
Instead of generating OR gate from Nand gates, the updated standard cell library had an OR gate.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog opt_check3.v
Command: synth –top opt_check3
Command: opt_clean –purge
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: The two multiplexers in the opt_check3.v are optimised as single 3 input AND gate. Because, one the inputs of the two multiplexers are zero they are optimised to AND gates as in opt_check.v.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog opt_check4.v
Command: synth –top opt_check4 Command: opt_clean –purge
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: The opt_check4.v design is simplified as an XNOR gate.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog multiple_module_opt.v
Command: synth –top multiple_module_opt Command: flatten
Command: opt_clean –purge
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
Command: write_verilog –noattr multiple_module_opt_netlist.v Command: !gvim multiple_module_opt_netlist.v
OBSERVATIONS:
The multiple_module_opt.v is optimised to a two input AND gate and two input OR gate using boolean logic optimization.
The U1 module is simplified to a.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog multiple_module_opt.v
Command: synth –top multiple_module_opt2 Command: flatten
Command: opt_clean –purge
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
Command: write_verilog –noattr multiple_module_opt2_netlist.v Command: !gvim multiple_module_module_opt2_netlist.v
OBSERVATIONS:
The synthesizer optimised the multiple_module_opt2.v using constant propagation optimization.
The synthesizer optimized the output to zero.
Command: iverilog dff_const1.v tb_dff_const1.v Command: ./a.out
Command: gtkwave tb_dff_const1.vcd
OBSERVATIONS: The q doesn’t change value when reset is low. Q will change value only with the
posedge of the clock.
Command: iverilog dff_const1.v tb_dff_const2.v Command: ./a.out
Command: gtkwave tb_dff_const2.vcd
OBSERVATIONS: The q value is always one.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const1.v
Command: synth –top dff_const1
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: As stated before, the D_flip_flop in the netlist is active_low. So, the synthesizer used an inverter to change rest from active_high to active_low.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const2.v
Command: synth –top dff_const2
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATION: ABC command ‘s result is indicating that there is no standard cell.
Command: iverilog dff_const3.v tb_dff_const3.v Command: ./.aout
Command: gtkwave tb_dff_const3.vcd
OBSERVATIONS: q=1 at every instant except at the moment in the above figure. So, the flipflop can’t
be optimised.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const3.v
Command: synth –top dff_const3
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: Because q cannot be optimised, the circuit remains unoptimized.
Command: iverilog dff_const4.v tb_dff_const4.v Command: ./.aout
Command: gtkwave tb_dff_const4.vcd
OBSERVATIONS: The q is always one. Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const4.v
Command: synth –top dff_const4
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: As the q is always one in this synthesis, there is no standard cell in the netlist.
Command: iverilog dff_const5.v tb_dff_const5.v Command: ./.aout
Command: gtkwave tb_dff_const5.vcd
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog dff_const4.v
Command: synth –top dff_const4
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: There is no optimization in this file synthesis.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog counter_opt.v
Command: synth –top counter_opt
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: The synthesis shows that q is connected to D through an inverter. So, for every posedge, they q will change. The synthesizer will ignore the counting of the remaining two bits.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog counter_opt2.v
Command: synth –top counter_opt
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: There is no optimization in this synthesis.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog counter_opt3.v
Command: synth –top counter_opt
Command: dfflibmap –liberty ../my_lib/lib/sky130_fd_sc_hd__tt_025C_1v80.lib Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
DAY 4:
Command: iverilog ternary_operator_mux.v tb_ternary_operator_mux.v Command: ./a.out
Command: gtkwave tb_ternary_operator_mux.vcd
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib
Command: read_verilog ternary_operator_mux.v Command: synth –top ternary_operator_mux
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
Command: write_verilog –noattr ternary_operator_mux_net.v
Command: iverilog ../my_lib/verilog_model/primitives.v ../my_lib/verilog_model/sky130_fd_sc_hd.v ternary_operator_mux_net.v tb_ternary_operator_mux.v
Command: ./a.out
Command: gtkwave tb_ternary_operator_mux.v
Command: iverilog bad_mux.v tb_bad_mux.v Command: ./a.out
Command: gtkwave tb_bad_mux.vcd
OBSERVTIONS: Clearly, the waveform shows that the verilog file is not working as a multiplexer.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog bad_mux.v
Command: synth –top bad_mux
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: write_verilog –noattr bad_mux_net.v
Command: iverilog ../my_lib/verilog_module/primitives.v
../my_lib/verilog_model/sky130_fd_sc_hd.v bad_mux.net.v tb_bad_mux.v Command: ./a.out
Command: gtkwave tb_bad_mux.vcd
OBSERVATION: THE ABOVE WAVEFORM CLEARLY INDICATES SIMULATION – SYNTHESIS MISMATCH CAUSED BY MISSING SENSITIVITY LIST.
Command: iverilog blocking_caveat.v tb_blocking_caveat.v Command: ./a.out
Command: gtkwave tb_blocking_caveat.vcd
OBSERVATIONS: Clearly, the output of the aORb is taking previous values to generate d.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog blocking_caveat.v
Command: synth –top blocking_caveat
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: write_verilog –noattr bad_mux_net.v
Command: iverilog ../my_lib/verilog_module/primitives.v
../my_lib/verilog_model/sky130_fd_sc_hd.v blocking_caveat_net.v tb_blocking_caveat.v Command: ./a.out
Command: gtkwave tb_blocking_caveat.vcd
OBSERVATION: Clearly, the waveform after synthesis indicates the simulation-synthesis mismatch caused by blocking-caveat.
DAY 5:
Command: iverilog incomp_if.v tb_incomp_if.v Command: ./a.out
Command: gtkwave tb_incomp_if.vcd
OBSERVATIONS:
Whenever i0 is high, the y is following i1.
Whenever i0 is low, the output y is latching to its previous value as shown in above two images. 3)This behaviour is due to inferred latch.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog incomp_if.v
Command: synth –top incomp_if
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib
Command: show
OBSERVATIONS: Both the simulation and synthesis are inferring a latch, when we designed a multiplexer.
Command: iverilog incomp_if2.v tb_incomp_if2.v Command: ./a.out
Command: gtkwave tb_incomp_if2.vcd
OBSERVATIONS:
When i0 is high, the output y is following i1.
When i2 is high and i1 is low, the output is following i2.
When both i2 and i0 are low, the output is latching to y.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog incomp_if2.v
Command: synth –top incomp_if2
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS:
Clearly, we can see the inferred latch on dot viewer.
The D_latch has active high enable. So, when i0 and i1 are low, the output of the nor gate becomes high. Then the latch becomes active.
Command: iverilog incomp_case.v tb_incomp_case.v Command: ./a.out
Command: gtkwave tb_incomp_case.vcd
OBSERVATIONS:
The output y is i0 when select is 00. When the select is 01, the output y is i1.
When the select bit [1] is high, the circuit latches to y value. In this y is zero.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog incomp_case.v
Command: synth –top incomp_case
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS:
1)The dot viewer is showing the latch with enable tied to select [1]. 2)The remaining part is the mux logic.
Command: iverilog comp_case.v tb_comp_case.v Command: ./a.out
Command: gtkwave tb_comp_case.vcd
OBSERVATIONS: The output y is following y when select is 10 or 11.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog comp_case.v
Command: synth –top comp_case
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS: Clearly, there is no latch and circuit is working fine in both simulation and synthesis.
Command: iverilog partial_case_assign.v tb_partial_case_assign.v Command: ./a.out
Command: gtkwave tb_partial_case_assign.vcd
OBSERVATION: Clearly, when select is 01, the x is latching to its value.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog partial_case_assign.v
Command: synth –top partial_case_assign
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATIONS:
1) The dot viewer clearly shows the latch for x and there is no latch for y.
Command: iverilog bad_case.v tb_bad_case.v Command: ./a.out
Command: gtkwave tb_bad_case.vcd
OBSERVATION: Clearly, when the select is 11, the output y is becoming 1.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog bad_case.v
Command: synth –top bad_case
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
Observation: There are no latches in bad_case.
Command: write_verilog –noattr tb_bad_case_net.v
Command: iverilog ../my_lib/verilog_model/primitives.v ../my_lib/verilog_model/sky130_fd_sc_hd.v bad_case_net.v tb_bad_case.v
Command: ./a.out
Command: gtkwave tb_bad_case.vcd
OBSERVATION:
The netlist simulations shows that the output y is taking i3, when the select is 11.
This is a simulation-synthesis mismatch. So, we need to avoid overlapping case while VERILOG coding.
Command: iverilog mux_generate.v tb_mux_generate.v Command: ./a.out
Command: gtkwave tb_mux_generate.vcd
OBSERVATION: We can see the waveforms of a 4:1 mulitplexer designed using for loop.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog mux_generate.v
Command: synth –top mux_generate
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATION: We can see that the synthesis has a latch. The latch just acts as a buffer.
Command: iverilog demux_case.v tb_demux_case.v Command: ./a.out
Command: gtkwave tb_demux_case.vcd
OBSERVATION: We can see that output is being selected based on the select line.
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog demux_case.v
Command: synth –top demux_case
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
Command: iverilog demux_generate.v tb_demux_generate.v Command: ./a.out
Command: gtkwave tb_demux_generate.vcd
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog demux_generate.v
Command: synth –top demux_generate
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show
OBSERVATION: In this lab, both demux_case.v and demux_generate.v has similar synthesis. However, the demux_generate.v can be scalable.
Command: gvim rca.v -o fa.v
Command: iverilog fa.v rca.v tb_rca.v
This command tells the simulator that fa.v is separate module but is called in rca.v. Command: ./a.out
Command: gtkwave tb_rca.vcd
Command: yosys
Command: read_liberty –lib ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: read_verilog fa.v
Command: read_verilog rca.v Command: synth –top rca
Command: abc –liberty ../my_lib/lib/sky130_fd_sc_hd tt_025C_1v80.lib Command: show rca
OBSERVATION: 8 FA MODULES ARE INSTANTIATED.
Command: write_verilog –noattr tb_rca_net.v
Command: iverilog ../my_lib/verilog_module/primitives.v
../my_lib/verilog_model/sky130_fd_sc_hd.v tb_rca_net.v tb_rca.v Command: ./a.out
Command: gtkwave tb_rca.vcd
OBSERVATIONS: There is no mismatch between simulation and synthesis.